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Synopsys Fusion Technology Enables Lower Power, Smaller Area, and Higher Performance on Samsung Foundry 7LPP Process with EUV
Wednesday, June 13, 2018

Synopsys Design Platform Certified using 64-bit Arm Cortex-A53 Processor

MOUNTAIN VIEW, Calif., June 13, 2018 /PRNewswire/ --


    --  Synopsys Design Platform with Fusion Technology((TM)) delivers power,
        performance, and area benefits for Samsung Foundry's 7LPP process with
        extreme ultraviolet (EUV) lithography technology
    --  Comprehensive full-flow support for single-exposure-based routing and
        via stapling for maximum design routability in Design Compiler(®)
        Graphical RTL synthesis, IC Compiler((TM)) II place-and-route, and
        PrimeTime(®) timing signoff
    --  Tool certification includes scalable 7LPP reference flow compatible with
        Lynx Design System using the 64-bit Arm(®) Cortex(®)-A53 processor for
        QoR optimization and flow validation

Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Foundry has certified the Synopsys Design Platform with Fusion Technology for 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology. The Synopsys Design Platform provides comprehensive full-flow 7LPP support for EUV single-exposure-based routing and via stapling to ensure maximum design routability and utilization while minimizing IR-drop. Synopsys' SiliconSmart(®) library characterization tool was key to developing the foundation IP used for this certification process and reference flow. Samsung Foundry has certified Synopsys Design Platform tools and the reference flow, which is compatible with the Lynx Design System with scripts for automation and design best practices. The reference flow is available through the Samsung Advanced Foundry Ecosystem (SAFE((TM))) program.

"Built through deep collaboration with Synopsys, this certification and reference flow for our 7LPP process will enable our mutual customers to achieve the best power, performance, and area for their designs," said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. "Our foundry customers can confidently ramp their designs to volume production on our most advanced EUV-based process using the proven Synopsys Design Platform with Fusion Technology."

"Our tools and reference flow collaboration with Samsung Foundry is focused on enabling designers to get the optimum quality of results with the highest confidence on Samsung Foundry's latest 7LPP process with EUV," said Michael Jackson, corporate vice president of marketing and business development for Synopsys' Design Group. "This scalable 7LPP reference flow based on the Synopsys Design Platform with Fusion Technology will allow designers to easily achieve their desired design and schedule targets."

The 64-bit Arm Cortex-A53 processor, based on the ARMv8 architecture, was used for quality of results (QoR) optimization and flow certification. Key tools and features of the Synopsys Design Platform 7LPP reference flow include:

    --  IC Compiler II place-and-route: EUV single-exposure-based routing with
        optimized 7LPP design rule support, and via stapling to ensure maximum
        design routability and utilization while minimizing IR-drop
    --  Design Compiler Graphical RTL synthesis: Correlation, congestion
        reduction, optimized 7LPP design rule support, and physical guidance for
        IC Compiler II
    --  IC Validator physical signoff: High-performance DRC signoff, LVS-aware
        short-finder, signoff fill, pattern matching, and unique dirty data
        analysis with Explorer technology, as well as in-design verification for
        automated DRC repair and accurate timing-aware metal fill within IC
        Compiler II
    --  PrimeTime timing signoff: Near-threshold ultra-low voltage variation
        modeling, via variation modeling, and placement rule-aware engineering
        change order (ECO) guidance
    --  StarRC((TM)) parasitic extraction: EUV single pattern-based routing
        support, and new extraction technologies such as coverage-based via
    --  RedHawk((TM)) Analysis Fusion: ANSYS(®) RedHawk((TM))-driven EM/IR
        analysis and optimization within IC Compiler II including via insertion
        and power grid augmentation
    --  DFTMAX((TM)) and TetraMAX(®) II test: FinFET-based, cell-aware, and
        slack-based transition testing for higher test quality
    --  Formality(®) formal verification: UPF-based equivalence checking with
        state transition verification

The certified, scalable reference flow compatible with Synopsys' Lynx Design System is available through the SAFE((TM)) program. The Lynx Design System is a full-chip design environment that includes innovative automation and reporting capabilities to help designers implement and monitor their designs. It includes a production RTL-to-GDSII flow that simplifies and automates many critical implementation and validation tasks, enabling engineers to focus on achieving performance and design goals. The SAFE((TM)) program provides extensively tested process design kits (PDKs) and reference flows (with design methodologies) that are backed by Samsung Foundry's certification.

About Fusion Technology
Synopsys' breakthrough Fusion Technology transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools, enabling designers to accelerate the delivery of their next-generation designs with the industry-best full-flow QoR and the fastest time-to-results (TTR). It redefines conventional EDA tool boundaries across synthesis, place-and-route, and signoff, sharing engines across the industry's premier digital design tools, and using a unique, single data model for both logical and physical representation. Fusion Technology enables one DNA backbone across the Synopsys Design Platform that includes IC Compiler II place-and-route, Design Compiler Graphical synthesis, PrimeTime signoff, StarRC extraction, IC Validator physical verification, DFTMAX test, TetraMAX II automatic test pattern generation (ATPG), SpyGlass(®) DFT ADV RTL testability analysis, and Formality equivalence checking. It provides Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion, resulting in the most predictable RTL-to-GDSII flow with the fewest iterations, as well as unsurpassed design frequency, power, and area.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software((TM)) partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15(th) largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at

ANSYS, ANSYS Workbench, AUTODYN, CFX, FLUENT and any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries. All other brand, product, service and feature names or trademarks are the property of their respective owners.

Editorial Contact:
James Watts
Synopsys, Inc.

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SOURCE Synopsys, Inc.

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